Reduce CW340 bootstrap SPI clock speed #28801
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AlexJones0
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Nov 21, 2025
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Looks okay to me, it makes sense for the current CW340 CI setup. I wonder if you could add a comment so that anybody without external connections to the TPM wires knows that they can safely bump this back to 5000000 bps?
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Also maybe you should add the |
The reduction is necessary due to increased bus capacitance introduced by external wires connected to the TPM SPI interface, which affects signal integrity. This change improves CW340 stability during bootstrap for CI tests. Signed-off-by: Douglas Reis <[email protected]>
jwnrt
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Nov 21, 2025
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The reduction is necessary due to increased bus capacitance introduced by external wires connected to the TPM SPI interface, which affects signal integrity. This change improves CW340 stability during bootstrap for CI tests.